Typical modern digital communications systems make use of many clocks, in order to operate the system elements. Typical such communications systems include mobile telephones, GPS receivers, and the like. Having accurate internal clocks is important, for example for signal acquisition, demodulation, and decoding purposes.
FIG. 1 illustrates the clocks present in a typical communications system. Firstly, a reference clock 12 from the communications modem, such as a cellular modem in the case of a cellular handset, may be provided, and which outputs a clock signal, CLK_MOD (2). This is a clock which may typically be switched on or off depending on the use of the communications system, in order to save power.
Additionally provided is typically a basic system clock, referred to as a real time clock 14. This provides a clock signal RTC (4). Typically, the frequency of such a clock is set to be 32 kHz, although other frequencies may be used.
Additionally, a communications system will usually have a very accurate master clock, typically located off chip, as shown by being located outside the outer dotted line in FIG. 1. The master clock will typically be a crystal oscillator (XO), or a temperature controlled crystal oscillator (TCXO) such as TCXO 16. Again, to save power the TCXO or XO may be switched off, when the communications system is not in use.
To generate a high frequency reference clock, needed, for example, for spread spectrum communications, a phase lock loop 18 is commonly used to generate the high frequency clock from the external oscillator 16. A phase lock loop typically comprises a phase and frequency detector (PFD) 182, which outputs a phase error signal to a low pass filter 184, the filtered phase error signal then being used to control a voltage controlled oscillator (VCO) 186. The output of the voltage controlled oscillator is taken as the high frequency clock signal, in this case CSS_REF (6), and is also fed back, typically via a frequency divider 188, to a second input of the phase and frequency detector 182. The first input of the phase and frequency detector 182 receives the reference clock from the external oscillator. The phase error signal output by the PFD 182 is dependent on the phase (and, initially, frequency) difference between the reference clock from the external oscillator and the frequency divided feed back clock. The phase lock loop acts to generate a higher frequency clock, based upon the reference clock input thereto. The operation of such a phase lock loop is well known in the art, and will not be described further.
Typically, the real time clock 14, which forms the basic system clock, will usually comprise a low precision oscillator, with an accuracy of typically between 20 to 100 parts per million (ppm). The other clocks in the system will typically have a much higher precision, between 0.05 to 2 parts per million, for example. The advantage of the real time clock, however, is that it is always switched on, whilst the communications system is powered up. That is, the operation of the clock is not dependent upon whether the communications system is actually operating i.e. to transmit or receive signals, like the other clocks. The real time clock signal is therefore always available to the communications system.
As mentioned, phase lock loops are often used to generate high frequency clocks based on the accurate external oscillator. However, phase lock loops can be very susceptible to a frequency deviation caused by an external interfering signal in a similar frequency band. For example, in the case where a strong interfering signal is present at a similar frequency to the clock output by the PLL, then that interfering signal can enter the feedback path of the PLL, causing the phase error signal generated by the phase and frequency detector 182 to become incorrect. In effect the interferer signal can capture the PLL, thus affecting the generation of the wanted clock, such as, in the example of FIG. 1, the communication subsystem reference clock CSS_REF. In many communications systems, if the high frequency clock within the system changes, then the overall time base used by the communications system will not be valid, and the communications system will fail. For example, in a GPS system, a GPS receiver would not be able to maintain track on satellites, and a position fix would not be able to be performed.
Heretofore it has been very difficult to actually detect within a communications system as to whether the generation of a clock signal is being affected by interference, such that the generated clock is no longer accurate. In this respect, the generated clocks are themselves typically the reference time bases for the other system components. It is known to be able to check the accuracy of clock signals using other, more accurate or higher frequency clocks. For examples, U.S. Pat. No. 6,442,704 and US 2005/0286670 give examples of such arrangements. However, these arrangements depend on the existence of high accuracy clock signals that themselves may be, unknowingly, suffering from either the same or different interference. As mentioned previously, the accurate generation of clock signals in a communications system is absolutely essential, and in particular for signal acquisition, demodulation, and decoding purposes. The ability to be able to check the accurate generation of clock signals in a reliable manner is therefore important.